`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:36:04 07/12/2015 
// Design Name: 
// Module Name:    MemInstArtesanal 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MemInstArtesanal(
	input clka,
	input [31:0] addra,
	output reg [31:0] douta
    );

reg [31:0] memoria[63:0];

initial begin
	memoria[0] = 32'b 00100001010010100000000000011111; //add inmediate - $10 = $10 + 15
	memoria[1] = 32'b 00100000000010110000000000001010; //add inmediate - $11 = $0 + 10
	memoria[2] = 32'b 00100000000011000000000000011010; //add inmediate - $12 = $0 + 26
	memoria[3] = 32'b 00100000000011010000000000001110; //add inmediate - $13 = $0 + 14
	memoria[4] = 32'b 00100000000011100000000000000010; //add inmediate - $14 = $0 + 2
	memoria[5] = 32'b 10101100000010100000000000000000; //store word memory[0] <- $10
	memoria[6] = 32'b 00000000000010100111100001000000; //Shift Left $15 = $10 << 1
	memoria[7] = 32'b 00010100000000000000000000000001; //Branch NE
	memoria[8] = 32'b 00010000000000000000000000000001; //Branch E
	memoria[9] = 32'b 00100000000011100000000000000010;
	memoria[10] = 32'b 00100000000011100000000000000011;
	memoria[11] = 32'b 10011100000000010000000000000000; //Load 
	memoria[12] = 32'b 00001000000000000000000000000000; //jmp al 0
	memoria[13] = 32'b 00100000000011100000000000000010;
	memoria[14] = 32'b 00100000000011100000000000000010;
	memoria[15] = 32'b 00100000000011100000000000000010;
	memoria[16] = 32'b 00100000000011100000000000000010;
	memoria[17] = 32'b 00100000000011100000000000000010;
end

always@(posedge clka) begin
	if((addra/4) < 64) douta = memoria[addra/4];
end

endmodule
